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Senior Design verification Engineer

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Senior Design verification Engineer

SENIOR DESIGN VERIFICATION ENGINEER

SiPearl is working on one of the most exciting and technically challenging

projects in Europe right now… designing the microprocessor powering

supercomputers in the European union and the rest of the world for the

years to come!

To accomplish its mission SiPearl needs verification engineers keen to

work across a wide range of technologies and on methodologies at the

state of the art. You will be involved in verification of products built

around the highest performance cores and the latest standard protocols

(AXI/CHI, PCIe, DDR, HBM…)

As a functional verification engineer, you will be interfacing with

architecture, design, physical implementation and software teams in order

to make sure that the systems that SiPearl is building are performing to

the highest level. Your work may involve high-level modelling, UVM,

HW/SW Co-Debug, Simulation Acceleration support… Opportunities to

learn and develop technically as well as personally are aplenty here!

RESPONSIBILITIES

As a startup, SiPearl offers an environment where you will have a visible

impact on the product development. You will report to the verification

manager and will have the opportunity to be a driving force of the

verification effort. Your day-to-day work will entail the following:


• Reading and analysing the system requirements and architecture

requirement documents


• Plan for functional verification activities for a given

subsystem/functionality


• Verification environment development and maintenance in

SystemVerilog/UVM/SystemC/C++


• Tests writing in embedded C and debug


• Participation to verification methodology improvements


• Project milestones and deliverables planning with respect to

functional verification within SiPearl and with external partners


• Organize work and deliverables between skills, internal and external

teams


• Opportunities for mentoring and training the next generation of

verification engineers


• Opportunities to manage teams from external partners

LOCATION

Barcelona (Castelldefels)

USEFUL TECHNICAL SKILLS

We are particularly looking for engineers with at least 4 years of

experience in:


• Verification of complex SoC or IP


• Experienced in:


• SystemVerilog/UVM/VHDL


• SystemC/C++


• Some previous experience in Firmware based verification is a good

to have


• Some knowledge of scripting languages like Bash/Perl/Python


• Use of verification management tools

Experience in the following are a plus:


• Experience in Firmware-based verification


• Knowledge in metrics-driven verification


• Use Git/Gitlab


• Insights of AMBA and other ARM Ips or standard peripherals like

PCIe, DDR, HBM …

All applications from individuals with some experience in FPGA/ASIC

development flows will be considered!

YOUR PROFILE

We are looking for team players, able to work with multiple cultures both

on site and remotely.

Being autonomous and flexible is mandatory. As a young and rapidly

growing company, we welcome people who have a team-building mindset

and who are eager to build the identity of the structure across multiple

sites! Of course, a good level of English, both written and spoken is

mandatory as we have offices and partners across the world.

There will be opportunities to gain experience in other fields of digital

systems engineering so engineers who want to develop a versatile and

cross-functional skillset, we welcome you!

CONDITIONS & BENEFITS


• Fixed salary and variable part to be defined on experience


• Restaurant tickets


• Private insurance 70% covered by SiPearl


• At least 2 day of homeoffice per week

Job Post 2:

SENIOR RTL DESIGN ENGINEER

SiPearl is working on one of the most exciting and technically challenging

projects in Europe right now… designing the microprocessor powering

supercomputers in the European union and the rest of the world for the

years to come!

Reporting to the HW team manager, you will oversee:


• Read and analysize the system requirement and architecture

requirement documents


• Work with architecture team to mature the design specifications for

further implementation


• Coding in HDL to implement desired functions based on design

specifications


• Design or integrate the testbench for design verification


• Generate design report to detail functions and behavior


• Create application guide for h/w and s/w integration


• Work with integration teams to participate in design integration


• Help model teams to build model of the design and get it integrated


• Work with verification teams to verify the design with module-test or

system-level-test


• Collaborate with firmware teams support developing firmware and

drivers


• Packaging the design into IP for future reuse


• Guide and review the juniors in the team as the mentor

REQUIREMENTS

You are or you have:


• At least 4 years of experience in digital HDL functional design or

integration


• Experience specifically in integrating digital designs for complex chip

or SoC including integration, synthesis, STA and DFT related activities


• Excellent knowledge in SystemVerilog and Verilog and at least two of

the following: C++, Python, Pearl, Gitlab


• Experience of using tools and script language for automated

integration


• Good knowledge using Synopsys tools (Spyglass, DC, Primetime)


• (Preferred) Experience of using Mentor tools (Questa-sim,

LEC), using AMBA and Arm IPs


• (Optionally) Skills in script design for automation


• (Optional) Working experience with AMBA and Arm IP designs or

peripherals like PCIe, HBM, DDR …

LOCATION

Barcelona (Castelldefels)

PROFILE

We are looking for team players, able to work with multiple cultures both

on site and remotely.

Being autonomous and flexible is mandatory. As a young and rapidly

growing company, we welcome people who have a team-building mindset

and who are eager to build the identity of the structure across multiple

sites! Of course, a good level of English, both written and spoken is

mandatory as we have offices and partners across the world.

There will be opportunities to gain experience in other fields of digital

systems engineering, so engineers who want to develop a versatile and

cross-functional skillset, we welcome you!

CONDITIONS & BENEFITS


• Fixed salary and variable part to be defined on experience


• Restaurant tickets


• Private insurance 70% covered by SiPearl


• At least 1 day of homeoffice per week